1. Field of the Invention
The present invention relates generally to semiconductor memory devices and a testing method therein, and more particularly, to a semiconductor memory device comprising an on-chip test circuit and a testing method therein.
2. Description of the Background Art
As the capacity of a semiconductor memory device is increased, the increase in test time becomes a serious problem. In an article by J. Inoue et al., entitled "PARALLEL TESTING TECHNOLOGY FOR VLSI MEMORIES", ITC Proceedings.,1987, pp. 1066-1071; an article entitled "TECHNOLOGY FOR INCREASING TEST EFFICIENCY SUITABLE FOR VERY LARGE CAPACITY MEMORIES", 1987 National Conference 165 of Semiconductor Materials Section of Institute of Electronics, Information and Communication Engineers of Japan, pp. 166, a parallel testing technology for VLSI memories, which reduces functional test time drastically, is proposed. All memory cells connected to a word line are simultaneously tested by introducing an on-chip test circuit
FIG. 1 is a circuit diagram showing a structure of a memory comprising an on-chip test circuit shown in the latter document. This memory comprises an m x n bit memory array having a plurality of memory cells arranged in a matrix, as shown in, for example, FIG. 2.
In FIG. 1, a test circuit 20 is connected to a memory array 10. In the memory array 10, a plurality of word lines and a plurality of bit line pairs are arranged intersecting with each other, memory cells being provided at intersections thereof. In FIG. 1, four word lines WLI to WL4 and two bit line pairs B1, B1 and B2, B2 are typically shown. The test circuit 20 comprises a write circuit 30, comparing circuits CP1 and CP2 and a detecting circuit 100. The write circuit 30 comprises N channel MOS transistors Q1 to Q4, a write control line WC, and write lines W and W. The comparing circuit CP1 comprises N channel MOS transistors Q5 and Q6, and the comparing circuit CP2 comprises N channel MOS transistors Q7 and Q8. The detecting circuit 100 comprises N channel MOS transistors Q9 and Q10, an inverter G1, and a precharge circuit 110.
In the above described document, a line test is proposed by which test time is significantly reduced. Description is now made on the line test. First, for example, "H" and "L" level data are respectively applied to the write lines W and W, and a potential on the write control line WC is raised to the "H" level. Consequently, the transistors Q1 to Q4 are turned on, so that potentials on the bit lines B1 and B2 become the "H" level and the potentials on the bit lines B1 and B2 become the "L" level. When a potential on the word line WL1 is raised to the "H" level, "H" level data are respectively written into memory cells Ml and M3. After writing, the potentials on the word line WL1 and the write control line WC are brought to the "L" level.
Thereafter, when the potential on the word line WL1 is raised to the "H" level, the data stored in the memory cells Ml and M3 are respectively read out onto the bit lines B1 and B2. Data on the bit line pairs B1, B1 and B2, B2 are amplified by a sense amplifier (not shown). In the case of the memory array 10 shown in FIG. 2, n-bit: data as amplified are read out onto the bit line pairs. Then, "L" and "H" level data are respectively applied to the write lines W and W.
When the data read out from the memory cells Ml and M3 are at the "H" level, the potentials on the bit lines& B1 and B2 become the "H" level, and the potentials on the bit lines B1 and B2 become the "L" level. Consequently, the transistors Q5 and Q7 are turned on, so that both potentials of nodes N1 and N2 become the "L" level. Therefore, the transistors Q9 and Q10 are turned off, so that the node N3 precharged in advance by the precharge circuit 110 is not discharged. Thus, an "L" level flag signal is outputted to a detection signal output line DS.
It is assumed here that the memory cell Ml, for example, is defective. In this case, the data read out from the memory cells Ml and M3 respectively become the "L" and "H" levels, although "H" level data were written in the memory cells Ml and M3. Consequently, the potentials on the bit lines B1 and B1 respectively become the "L" and "H" levels. When "L" and "H" level data are respectively applied to the write lines W and W, the transistor Q6 is turned on, so that the node N1 is charged at the "H" level. Consequently, the transistor Q9 is turned on, so that the node N3 is discharged at the "L" level. As a result, an "H" level flag signal indicating an error is outputted from the detection signal output line DS.
As described in the foregoing, in the above described line test, data are applied to the write lines W and W and then, the data are written into a row of memory cells connected to a selected word line. As a result, the same data are written in the row of memory cells. The data are read out from the row of memory cells, and data opposite to the data previously applied to the write lines W and W are respectively applied to the write lines W and W. When data read out from a row of memory cells all match data previously written in the row of memory cells, an "L" level flag signal is outputted from the detection signal output line DS. On the other hand, when at least one memory cell out of a row of memory cells connected to one word line is defective so that data read out from the memory cell does not match data previously written in the memory cell, an "H" level flag signal is outputted from the detection signal output line DS.
As described in the foregoing, in the memory comprising an on-chip test circuit shown in FIG. 1, all memory cells connected to one word line are simultaneously tested. Thus, significant test time reduction is expected.
However, in this memory, the write control line WC and the write lines W and W common to all the bit line pairs are provided, whereby only the same data can be written in a row of memory cells connected to one word line. More specifically, a pattern of test data inputted to a row of memory cells is formed of "H" or "L" level data. Therefore, leakage between adjacent memory cells, or the like can not be detected by writing different data into the adjacent memory cells. Thus, in the memory shown in FIG. 1, detection sensitivity of the defective memory cell is decreased, although the test time can be reduced by the line test.